Clock-pulse extractors conventionally used at receiving stations of PCM transmission systems comprise voltage-controlled oscillators whose output voltage is a pulse train fed back to a phase comparator, also receiving the incoming signal, which forms part of a phase-locking loop serving to suppress rapid phase excursions of that signal in the oscillator output. The phase comparator delivers a voltage proportional to phase differences between the generated pulse train and the digital signal, this voltage being delivered to a control input of the oscillator by way of a low-pass filter. Up to a certain limiting jitter frequency, which for clock-frequency stabilization should be as low as possible, the generated pulse train still follows the phase shifts of the signal. Thus, an imperfect phase-jitter suppressor of this type may conceivably be used in a sync-pulse extractor designed to preserve the original phase excursions, provided the limiting jitter frequency could be sufficiently raised for this purpose. Such a modification, however, would entail considerable circuital complications as higher jitter frequencies would require a larger loop amplification which is essentially supplied by the oscillator itself and which would have to take into account a variable transfer coefficient of the phase comparator; this coefficient is an approximately linear function of the number of incoming pulses of relatively high voltage (data bits of logical value "1") in a given number of bit periods and therefore depends on the instantaneous bit pattern so that a separate control circuit would be needed in order to keep the loop amplification constant. The design of a suitable phase comparator, responding only to data-word configurations which begin with such "one" bits, is also relatively complex.